BENEFITS
Fastest time to market
Using pre-built and qualified Wavious chiplets for IO, Compute, Connectivity, Memory, Camera, Display, Machine learning and more allows for full solution chip systems in a fraction of the time of a standard SOC development cycle.
Rapid System Integration
(6mo vs 2yr)
Custom/semi-custom chiplet design
Using Wavious template based solutions allows rapid custom and semi-custom chiplet design by wavious service group or customer to create only what is needed and to be used with other off the shelf Wavious chiplets for full SIP solutions.
Lower Product Development Costs
Using pre-built and qualified Wavious chiplets drastically reduces the verification, integration and design of systems due to testing, verification, IP porting, and system bring up not being needed to be redone for everything with a process change. Only the chiplet under design change needs to go through the full design process.
Lower Production Cost
Chiplets have much smaller footprints and are process optimized then combined to create the SIP(system in Package) with the same system solution as a monolithic SOC. This leads to not only silicon costs cheaper for older process nodes but also much better over yields.
Competitive Power and Performance
Using Wavious Power Management Unit(WPU) with high speed multi-phase EVR allows for optimum power delivery to reduce corner sets and creates a more optimized design for all chiplets systems. Best in class Wavious connectivity IP allows for any connectivity for optimized power and performance based on system needs
SEIZING THE MARKET
Existing Chiplet solutions have been optimized for Compute applications that do not address cost and power sensitive systems
Existing ASIC companies have long and expensive development cycles
There is currently no other solution that provides the TTM and flexibility to address cost sensitive vertical markets
Chiplets into SiP Creation
Wavious and/or partners chiplets from the Wavious chiplet marketplace can be mix and matched to create SIP solutions for various AI/ML markets based on the customers need and use case.
Market Outlook
Set to exceed an annual growth rate of more than 40%, chiplets represent an innovative, emerging approach that help advance new packaging technologies, new design strategies and new materials.
Chiplet HUB
Power Management
Memory Access
Connectivity
Machine Learning
WAVIOUS SiP SOLUTIONS
Click on the SiP below to view a detailed image.
WAVIOUS SERVICES
Wavious services can help customers create fully custom chiplets using in house IP and/or customer IP/Design and can take it from conception to completion. Wavious services can also modify existing chiplets adding customer defined design to create semi-custom chiplets or can provide the Wavious Chiplet Platform template that a customer can place in their own chip to allow access to all of wavious and partners chiplets in the marketplace.
ABOUT US
Established in 2015, Wavious now has 25+ engineers between San Diego and Raleigh. The Wavious Founding Team has collectively led multiple successful startups. Each member is well-known and accomplished in the marketplace with more than 25 years of experience on average.
Benny Malek — CEO/President
Qualcomm, Rapid Bridge, Nurlogic
Jason Thurston — COO
Qualcomm, Rapid Bridge, ARM, Cadence
Massih Tayebi — Board Member
CEO/Founder – Bridgewest Group
Hanan Cohen — CTO
Qualcomm, AppliedMicro, Conexant, Metalink
Mark Vilas — SVP, Chiplet Design
Qualcomm, RapidBridge, ARM, Apple
Mike Clovis — SVP, Chiplet Architect
Qualcomm, Applied Micro, Yuni Networks, Intel
Ken Arcudia — Fellow
Qualcomm, Cadence
Nur Sambawa — Fellow
Qualcomm, RapidBridge, ARM
News
July 26, 2021
Wavious is excited to announce the release of S-Link: a lightweight chiplet/chip-to-chip controller
S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication. S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
S-Link is released under the MIT license.
Various versions of S-Link have been taped-out in the WLP120 and WH440 chiplets as part of the Wavious Chiplet Platform ecosystem. Several versions have also been implemented in FPGA for testing, validation, and prototyping.
We are strong believers in OpenSource hardware and Software and Wavious is dedicated to making significant contributions to the OpenSource community. OpenSource HW and Chiplets are both necessary to remove barriers to entry and to drive innovation in system design.
About Wavious:
Wavious develops a rich catalog of chiplets targeting solutions for compute and AI/ML, from Edge and Core to Cloud. Wavious Chiplet Platform enables our customers to achieve near FPGA flexibility and TTM with ASIC power, performance and cost.
The Wavious Chiplet Platform enables a chiplet-based marketplace to grow and innovate, less encumbered by traditional SoC limitations in process, power, time to market, and development cost.
July 20, 2021
Wavious is excited to announce the release of OpenSource LPDDR4x/5 PHY hardware and software IPs under the Apache 2.0 license
We are strong believers in OpenSource hardware and Software and Wavious is dedicated to making significant contributions to the OpenSource community. OpenSource HW and Chiplets are both necessary to remove barriers to entry and to drive innovation in system design.
The Wavious DDR (WDDR) Physical interface (PHY) is designed to be a scalable DDR PHY IP that meets high performance, low area and low power requirements across multiple JEDEC DRAM protocols. Initially targeting LPDDR4x and LPDDR5, the WDDR PHY supports JEDEC LPDDR protocols and a DFI5.0 compliant interface.
Features
LPDDR4x @4266 Mbps
LPDDR5 @6400 Mbps
Dual rank support
DFI5.0 compliant Memory Controller interface
Integrated RISC-V MicroController Unit (MCU) with embedded SRAM
Embedded training buffer
Embedded calibration logic
Embedded PLL
Per-bit deskew
https://lnkd.in/ghnRRAU
https://lnkd.in/gdiz6ys
The WDDR PHY IP has been taped-out in the WLP120 chiplet as part of the Wavious Chiplet Platform ecosystem.
About Wavious https://wavious.com/
Wavious develops a rich catalog of chiplets targeting solutions for compute and AI/ML, from Edge and Core to Cloud. Wavious Chiplt Platform enables our customers to achieve near FPGA flexibility and TTM with ASIC power, performance and cost.
The Wavious Chiplet Platform enables a chiplet-based marketplace to grow and innovate, less encumbered by traditional SoC limitations in process, power, time to market, and development cost.
July 5, 2021
Wavious announces the availability of WPM100: Wavious Power Management chiplet
WPM100 provides power management and clocking solution for next generation, high performance chiplet based systems, in a single die, 2.0mm x 1.8mm.
WPM100 is designed to meet the precise voltage and fast transient requirements of high-performance circuits.
This versatile solution is suitable for Egde, mobile and compute systems.
– high switching-frequency DC-DC regulators
– Integrated LDOs
– Integrated PLLs can generate a wide range of clock frequencies, up to 5GHz, available on 3 differential output drivers.
– PCIe Get 3/4/5 refclock generation
– Data converters
– Xtal oscillator
Each WPM100 can provide up to 15A total current and up to 12 power domains.
WPM100 works seamlessly with WTM monitors to provide an optimal supply level and improve PPA
WPM100 greatly reduces BOM, PCB area, complexity, and cost compared to external Power management ICs ( PMIC)
June 25, 2021
Wavious tapes-out the first two chiplets from its portfolio:
Host chiplet (WH440) and LPDDR4x/5 connectivity chiplet (WLP120).
WH440 is housing four 64-bit RISC-V app processors, management core, caches, interrupt controller, memory management unit, memory protection unit, Ethernet, UART and connectivity to FPGA.
WH440 features four extension ports (WTM) based on Wavious proprietary WLINK die-to-die interface. Each WTM supports throughputs of up to 56GB/s at low latency. The extension ports enable our customers to add features such as high-speed connectivity (PCIe, SATA, USB, etc) , multimedia (CSI, DSI, etc) memory interface (DDR, LPDDR, HBM, GDDR etc) or co-processors, such as GPU, ML/AI accelerator, ISP etc.
WLP120 contains LPDDR4x/5 memory controller and two channel LPDDR4x/5 PHY to provide connectivity to main DRAM memory.
The SW stack has been developed to boot, train entire system, and runtime manage it. This system is capable to run RTOS and Linux OS.
