Advanced Chiplet Platform

Solutions for Compute and AI/ML, from Edge and Core to Cloud

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Wavious Chiplet Platform has a feature rich catalog of mix and match plug and play chiplets targeting solutions for compute and AI/ML, from Edge and Core to Cloud. Using our custom ultra-low power and high bandwidth die-to-die templates allows our customers to achieve near FPGA flexibility and TTM with ASIC power, performance and cost. The Wavious Chiplet Platform enables a chiplet-based marketplace to grow and innovate, less encumbered by traditional SoC limitations in process, power, time to market, and development cost.

Fastest time to market

Using pre-built and qualified Wavious chiplets for IO, Compute, Connectivity, Memory, Camera, Display, Machine learning and more allows for full solution chip systems in a fraction of the time of a standard SOC development cycle.

Rapid System Integration
(6mo vs 2yr)

Rapid prototyping or expansion of systems by selecting dies from a rich catalog of Wavious chiplets that will meet customer system performance and feature requirements.

Custom/semi-custom chiplet design

Using Wavious template based solutions allows rapid custom and semi-custom chiplet design by wavious service group or customer to create only what is needed and to be used with other off the shelf Wavious chiplets for full SIP solutions.

Lower Product Development Costs

Using pre-built and qualified Wavious chiplets drastically reduces the verification, integration and design of systems due to testing, verification, IP porting, and system bring up not being needed to be redone for everything with a process change.  Only the chiplet under design change needs to go through the full design process.

Lower Production Cost

Chiplets have much smaller footprints and are process optimized then combined to create the SIP(system in Package) with the same system solution as a monolithic SOC.  This leads to not only silicon costs cheaper for older process nodes but also much better over yields.

Competitive Power and Performance

Using Wavious Power Management Unit(WPU) with high speed multi-phase EVR allows for optimum power delivery to reduce corner sets and creates a more optimized design for all chiplets systems.  Best in class Wavious connectivity IP allows for any connectivity for optimized power and performance based on system needs


Existing Chiplet solutions have been optimized for Compute applications that do not address cost and power sensitive systems

Existing ASIC companies have long and expensive development cycles

There is currently no other solution that provides the TTM and flexibility to address cost sensitive vertical markets

Market Outlook

Set to exceed an annual growth rate of more than 40%, chiplets represent an innovative, emerging approach that help advance new packaging technologies, new design strategies and new materials.



Chiplet revenue is expected to expand to $57 billion in revenue by 2035


Percent Growth

Annual growth from adoption – $645 million in 2018 and expected to be nine times larger by 2024 at $5.8 billion


Wavious services can help customers create fully custom chiplets using in house IP and/or customer IP/Design and can take it from conception to completion. Wavious services can also modify existing chiplets adding customer defined design to create semi-custom chiplets or can provide the Wavious Chiplet Platform template that a customer can place in their own chip to allow access to all of wavious and partners chiplets in the marketplace.

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Established in 2015, Wavious now has 25+ engineers between San Diego and Raleigh. The Wavious Founding Team has collectively led multiple successful startups.  Each member is well-known and accomplished in the marketplace with more than 25 years of experience on average.